What is Cool Verification?
Benefits of Early Random Regressions

Is There a Usability Problem in Verification?

In an article entitled The Usability of Open Source Software, David M. Nichols and Michael B. Twidale argue that many open source software packages suffer from a lack of concern over the usability of their program to the average Joe User.  This got me thinking about whether the usability of open source software had any relation to the usability of EDA software.  It's well known that there are still a lot of organizations out there writing Verilog/VHDL testbenches years after they stopped being state-of-the-art.  The number of reasons for this are diverse and I won't attempt to address them all here.  One possibility may be that it can be a pain in the ass to get some Verilog simulators installed and running let alone integrate them with tools such as Specman, Vera, Debussy, Simvision, etc. 

Some EDA vendors are offering integrated solutions which lovingly lock a user into a contract buying all of their tools from a single source.   Of course, depending on the tool set you may get stuck using a less than optimal combination of  software packages. 

The big deal these days is SystemVerilog.  One of the benefits it's supposed to offer is the ability to do your design and verification in a unified language which has been integrated into the simulator core to offer you, the verification engineer, a seemless view of your little piece of the world.  Will it work?  Possibly.  I'm curious though - did anyone ever bounce these ideas off of a group of usability experts?  Might be an interesting question to pose to your local apps engineer.

 

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