Cool Verification

In an article entitled The Usability of Open Source Software, David M. Nichols and Michael B. Twidale argue that many open source software packages suffer from a lack of concern over the usability of their program to the average Joe User.  This got me thinking about whether the usability of open source software had any relation to the usability of EDA software.  It's well known that there are still a lot of organizations out there writing Verilog/VHDL testbenches years after they stopped being state-of-the-art.  The number of reasons for this are diverse and I won't attempt to address them all here.  One possibility may be that it can be a pain in the ass to get some Verilog simulators installed and running let alone integrate them with tools such as Specman, Vera, Debussy, Simvision, etc. 

Cool verification you ask? Since when? Though most senior managers will be happy to tell you how much they value their verification team, it's likely that a majority of them have no idea what the team does. What they do know is that they have a sneaking suspicion the work done by the verification team could somehow be done by the design or software group. This is not universally true, but it happens enough to make verification one of the less appealing computer engineering related jobs to new grads. It also can make the job unappealing to those of us already practicing the profession. So what's a depressed, overworked, unappreciated verification engineer to do?