Cool Verification

Link to Accellera Video

For some reason, the video I embedded in yesterday's blog post didn't show up in the email that many of you receive. Here is a direct link to my video on how to participate in the Accellera VIP-TSC UVM effort.

Quick Video: Signing Up to Participate in the Accellera UVM Effort

I've been looking into doing some online videos recently, and thought it would be fun as a test to show how simple it is for non-members to participate in the Accellera Verification IP technical subcommittee UVM development effort.

Signing Up to Participate in the Accellera UVM Effort (direct link)

Keep in mind this is the first time I've created a web video... constructive comments or questions are very much appreciated!

UVM Register Package Survey Results

A little over a month ago I sent out a request for your feedback on the possibility of adding a standardized register package to the UVM. Over the next 10 days I received 119 entries, 107 of which I consider valid (meaning they included an apparently real name and company email address, and did not appear to be duplicate submissions). Those 107 entries came from 63 different companies. The goal of the survey was to allow me to provide better input into the Accellera Verification IP TSC on whether a register package should be part of the UVM at some point.  The survey included the following questions:

1. Which SystemVerilog register package do you currently use?
• Cadence
• Mentor
• Synopsys
• Multiple
• Home grown
• None
• Other 
2. How important is it that the UVM contain a register package?
• Critical - we won't adopt the UVM without it
• Important - should be in the first release, but would be satisfied with the UVM even without this feature
• Low - Happy with whatever the TSC comes up with
• Don't care at all 
3. Would you be willing to delay the release of the UVM so that it could include a register package?
• Yes
• No
• Don't Care 

Many respondents also included comments. I’m going through those comments and will share them once I have a chance to scrub them of any personally identifying information. So, without further ado, here are the results. Values are listed as the number of responses for each answer.

Surprise, surprise... the "UVM-EA Kit" is already out of date!

Just to update everyone on the warning I posted last week. As expected, the current state of the Unified Universal Verification Methodolgy (UVM) library has changed such that the UVM-EA "kit" that was announced last week is already out of date. Actually, to be precise, the kit was never "in date", if that's even a valid phrase. But things have moved forward even in the last few days. If you're looking for information on the UVM, my recommendation is to be patient. Things are changing on a weekly basis, and the only way to stay on top of things for now is to start becoming involved with the Accellera VIP TSC. If you'd like to find out how to participate, please let me know and I'll fill you in on all the gory details.

EDA Vendors: Do More With Less

This post is for all of those lonely EDA vendors out there, wondering whether or how they're going to attract customers at the upcoming Design Automation Conference. You may have heard of Xuropa. Xuropa started out a couple of years ago focused on two things - creating an EDA social community and a related capability for vendors to showcase their products. Recently, they appear to have dropped the social networking aspect and really focused on enabling vendors to demonstrate their products via on-demand access to vendor "labs". The labs are basically controlled environments where users can actually run tools with all of the relevant files, licenses, and configuration already set up, without having to actually install anything on their own servers. 

How is this related to DAC?  As you may have guessed by now, Xuropa's online labs could be used to demonstrate your tools to customers on the DAC floor with only a network-connected laptop. Any heavy lifting required to run tools can be done on the Xuropa servers. Xuropa is giving away a free Xuropa Cloud Application Server and Collaboration Environment to the person with the best tip on how to "do more with less". If you're an EDA vendor planning to attend DAC, you'll want to check out Xuropa's "Do More With Less" contest for information on how to win.

Warning: The UVM "Early Adopter" (UVM-EA) release does not exist yet!

Some of you may have seen an announcement on Friday describing an early adopter kit of the UVM "based on the Accellera Verification IP Technical Subcommittee (VIP-TSC) decisions to date". Being a member of the Accellera VIP-TSC myself, I can assure you that the detailed technical contents of the purported "EA" release are still in flux. Anyone announcing such a release, even as a "kit" provided to allow users "to confidently start the process verifying your OVM products offerings in an UVM environment" is at best, misinformed about the current state of the UVM development effort and at worst endeavoring to hamper progress of the UVM. 

Consider yourselves warned.

One other point worth mentioning is that, at present, the UVM will be based on the OVM 2.1.1 code base but will only be reasonably backward compatible[*] with the OVM 2.0.3. Of course, this is subject to change based on future committee votes. I wish I didn't have to say this, but anyone telling you otherwise is probably trying to sell you something... 

For those of you who submitted responses to my register package survey, I've tabulated the results but am still working on anonymizing comments so I can share the details with Cool Verification readers and the VIP-TSC. Stay tuned!

[*] Updated since the original post - the UVM will not actually be directly backward compatible with any version of the OVM. Names of classes will be changed, some implementation details may be changed or deprecated, etc. Best to wait for official word from Accellera on what the first release of the library will look like.

Updated: Link to UVM Register Package Survey

Update March 26, 2010: The UVM register package survey is now closed. I am working on compiling the results from 107 valid responses. Stay tuned!

Hi everyone. Last night I wrote a post describing the debate over whether or not to include a register package in the UVM. The link to the survey was broken if you read the post in your email client or Google Reader. For those of you who couldn't get the link to work, try this direct link to the survey. I've gotten some very interesting feedback so far - keep it coming!

Register Packages and the UVM

Update March 26, 2010: The UVM register package survey is now closed. I am working on compiling the results from 107 valid responses. Stay tuned!

Updated 3/10/2010: Survey link wasn't working from email version of this post. Added a second link.

Many of the Accellera VIP TSC members are in Marlborough, MA this week discussing what features should be part of the first release of the new UVM (Unified Universal Verification Methodology). For those of you who are not familiar, the UVM is meant to be a SystemVerilog library supported by all three vendors. It will be based on the OVM 2.0.3 and will include support for features from other methodologies as we on the committee see fit. 

One of the hot topics during the discussions today was whether the UVM should contain a register package. I believe most of the vendors agree that such a common package is needed. They don't all agree on what form it should take (Cadence, Mentor, or Synopsys version) or when this package should be included in the UVM. For example, is a common register package important enough to delay the release of the UVM 1.0? Should it be based on an existing package or should the vendors attempt to merge their implementations?

Based on these questions, I have a favor to ask of you, my loyal readers. If you have a couple of minutes, please fill out the UVM Register Package Survey (UPDATE 3/10/2010: If that link to a pop-up version of the form doesn't work try this direct link to the survey) and let me know what you think about register packages and the UVM! I'll share the information with the VIP TSC. Also feel free to comment on this post or send me a private email at jl at coolverification dot com.

Some of you may wonder why I ask for company name and email address on the form. These types of surveys have a history of vote packing... I want to make sure I can verify that votes are from real people and not somehow the result of any shenanigans.  If anything looks suspicious, or if I have questions about your comments, I may contact you. I will absolutely not use this info for any other purpose.

Thanks in advance for all your help.

What Keeps You Up at Night?

For those of you who have not been paying attention, DVCon 2010 starts next week. In a previous post I described several events I'll be involved with except for one very important item.  This year I will be moderating the newly dubbed Industry Leaders Panel right after Lip-Bu Tan's keynote address.  The panel starts at 3:30pm on Wednesday, February 24.

Why am I hosting the panel this year? As it turns out, David Letterman, John Stewart, and Hugh Jackman were not available (click the link then scroll down and watch the video), so the DVCon steering committee was stuck with me ;-).

This year’s panel will ask the panelists “What Keeps You Up At Night?” and other pressing questions about what they see as the market’s challenges and opportunities. There will, as usual, be a no-holds-barred question and answer period. The panel will be made up of senior managers and directors from some of the world's top semiconductor companies (large, medium, and small), along with the analyst and consultant perspectives.

• Steven Gary - Numetrics Management Systems, Inc.
• John Goodenough - ARM Ltd.
• Sheela Pillai - Advanced Micro Devices, Inc.
• Jim Crocker - Paradigm Works, Inc.
• Victor Melamed - Ambarella

I would very much appreciate and enjoy any public or private comments you would like to share with me about what keeps you up at night on the types of projects you work on. I'm sure those of you approaching tapeout will have a long list! Also, I would like to make the panel as interactive as possible, and will collect any questions you'd like me to ask the panelists on your behalf. Feel free to post comments to this post or mail me at jl at coolverification dot com.

Thanks all, and I look forward to seeing you at DVCon next week!

Motivation for the UVM

In the beginning, there was SystemVerilog, and it was good. Through it some testbenches were made; without it other testbenches were made. In SystemVerilog was light, but also darkness in the form of a set of missing features that had to be implemented as library on top of verification languages by each user and also in the form of a lack of interoperability of language features between simulators.

To address the missing features there came a verification methodology sent from Synopsys; its name was VMM. The URM from Cadence and the AVM from Mentor came also and later merged to form the OVM, so that through them all engineers might believe in verification libraries.  The libraries did not completely address users’ concerns, but they did serve to validate users’ concerns as valid and worthy of consideration.

The libraries were the solution, and though the solutions were made through them the verification community did not recognize them as the solution because interoperability had not been solved.

Cool Verification 1:1-15 … ;-)

Ahem… As many of you are aware, the Accellera Verification IP Technical Subcommittee (VIP TSC), of which I am a member, is currently working on creating a unified universal verification methodology (UVM) that will be supported by the big three EDA vendors.  Ostensibly the library is being created so that users don’t have to make a (potentially limiting) choice between the OVM and VMM, but can instead use a library that is considered an industry standard. Sounds good, right? I’m going to make the potentially controversial claim that very few semiconductor companies actually care about using an industry standard methodology.