Cool Verification

Free Panel, and Photos from DVCon 2011 Day 2

Just a reminder, my Wednesday panel "Making Great Products Great" is free and open to the public. You just need to register for a free "Exhibit Only" pass either on the DVCon website or at the registration desk at the conference.

Also, for your viewing enjoyment, here are some photos from Day 2 of DVCon.

California Academy of Sciences Photos

On Sunday I visited the California Academy of Sciences in San Francisco. Click on the photo below to view some snapshots from my trip!

DVCon 2011: What engineers don't know about making great products

Those of you who attended DVCon last year may recall my panel "What Keeps You Awake at Night?". In that panel (check out the great writeup by Richard Goering for details) we brought together expert panelists on the front lines of chip design and verification to address the greatest concerns facing product development. This year, were taking things a step further and asking the folks who are the driving force behind successful product development to share their insights as part of my panel, "Making Great Products Great".  The panel will be held on Wednesday, March 2 at 3:45pm at the DoubleTree Hotel in San Jose. The panel is free to the public. Attendance simply requires filling out the free "Exhibits Only" DVCon registration.

DVCon 2011 Starts with a Bang: UVM Tutorial

It's that time of year - DVCon 2011 starts today. This is the 5th year I've attended DVCon, and today I saw something I haven't seen in prior years - a packed double-size room full of engineers anxiously awaiting the start of the UVM Tutorial sponsored by Accellera. 

The tutorial will cover the basics of the UVM, the new UVM Phasing mechanism, TLM, Sequences and Configuration, and the new UVM Register Package. Phasing has changed significantly in the UVM 1.0 release, as have sequences, configuration, and the register package... well, let's just say if you're interested in using the UVM this tutorial will be a great way to get caught up on what's new since the OVM 2.1.1.

I'll be in San Jose through Wednesday evening and would love to meet those of you attending the conference. Please flag me down and say hello! You can also follow me on Twitter, or follow the Twitter stream for all DVCon attendees using the #dvcon hash tag.

Virtual Panel Discussion: System Level Verification on Thursday, November 18

Just wanted to give everyone a heads up that I'll be participating in an online panel discussion as part of the EE Times System-on-a-chip 2.0 virtual conference next Thursday, November 18. 

http://www.eetimes.com/VirtualShows/Soc?p=Program

Information about the panel is below. I look forward to "seeing" you there!

Time: 4:30 pm - 5:30 pm EASTERN TIME

Verification is the single biggest challenge in the design of SoC devices and reusable IP blocks. There is a tremendous variety of software and hardware-assisted verification technologies available, but which will be the most effective for a particular project? What special verification tools and flows are available for ASIC and FPGA-based SoCs? Can point tools address any "EDA holes" in the large ASIC- and FPGA-based SoC design flows? Architecture-related verification, RTL debug, formal verification, and hardware-assisted verification technologies will all be considered in this session.

Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive

Panelists:

• JL Gray, Vice President, Verilab, Inc.
• Jack Donovan, Founder, SystematIC Design
• Brian Bailey, President, Brian Bailey Consulting
• Rajeev K. Ranjan, Chief Technology Officer, Jasper Design Automation

 

Pat Pistilli Selected to Receive Phil Kaufman Award

I've just received word that this year's Phil Kaufman award will be given to Pat Pistilli. Pat "will receive this year’s Phil Kaufman Award for pioneering the electronic design automation (EDA) industry and building the Design Automation Conference as its premier showcase and networking platform." I had an opportunity to meet and interview Pat at DAC in 2009. That interview definitely stands out as one of the highlights of the last 5 years I've been blogging on Cool Verification. Given my relatively short time in the EDA industry, it was fascinating to hear about what was going on back in the late 1950s and early 1960s when engineers were just starting to realize that it could be possible to create tools to automate computer design. From my interview with Pat:

'The now-obvious question that occurred to Pat and engineers at other companies at the time was, “What if a computer program could be written to automate the work currently being done by hand?” In theory, the computer ought to be able to do a better job, if only it was possible to enter the design into the computer in the first place.'

I'd like to extend my congratulations to Pat and thank him for his lifetime dedication to EDA. The dinner honoring Pat will be held Tuesday, October 12, at the San Jose Marriott Hotel in downtown San Jose.

Pat Pistilli, 2010 Phil Kaufman Award Winner

DAC 2010 Denali Party Photos

I've just posted my photos from this year's Denali party. Even if Cadence keeps the party going next year, it just won't be the same. Enjoy!

DAC 2010: My Personal "Must See" List

It's summertime, and in the EDA world, that can only mean one thing - it's time for the Design Automation Conference. I've been attending DAC since 2007, and for the second time since then DAC is in Anaheim, California. One of the things I find the most difficult about DAC is keeping track of what is going on when, so I thought I'd share what I've come up with so far with all of you. First, here are the events I will personally be participating in:

Tuesday

• 9a-noon: Synopsys Interoperability Booth
• 1:30p - Conversation Central: Verifying the Universe
  • I'll be hosting a conversation with Tom Alsop and Hillel Miller about the UVM development effort. The conversation will be streamed live, and you'll be able to call and ask questions if you're not able to attend in person.

Wednesday

• 4:30pm - Moderating the Pavilion Panel: SoC Verification - Are we there yet?

In addition to these events, I've got the following public sessions penciled in on my calendar. Given the complexity of grabbing events from the DAC website and adding them to my calendar, I'm certain I've forgotten an item or two.

UVM-EA Release Details

As I mentioned earlier in the week, the Universal Verification Methodology – Early Adopter release (UVM-EA) was announced on Monday and can be downloaded from the Accellera website. The process for putting together this release has been both exhilarating and frustrating, and it has highlighted (at least for me) the potentially transformative impact wide adoption of this library could have on the industry. Many users, from those with the most basic skills to those with the most advanced, have held off selecting a commercially available verification methodology for SystemVerilog. Initially, this may have been because they did not want to be locked in to a specific SystemVerilog simulator, though until recently (and, to be honest, still somewhat today), it was extremely difficult to write code that compiled on all three major simulators regardless of methodology. Some felt the VMM and OVM were too complex; others felt the libraries were ill-suited to their particular needs. 

Though I doubt anyone is going to stop what they’re doing and adopt the UVM mid-project, I believe engineers starting new verification efforts will take a serious look at the UVM.

UVM-EA Release Now Available

Just a quick note - the Universal Verification Methodology Early Adopter (UVM-EA) release is now available on the Accellera website. I'll post additional details on what the release includes later today.