Cool Verification

DAC, Accellera and Web 2.0

It's been awhile but don't worry, I'm still here!  If you'd like to see what I'm up to in real-time feel free to check out my Twitter feed (also from the Cool Verification homepage).  I'm testing out Twitter (and some other new web apps such as Jott and Remember the Milk) in preparation for DAC and apparently as a way to convince myself and my wife (ok, just my wife) that I need an iPhone.  I've also got some cool things to announce about Verilab and our activities at DAC this year - look for more in the next week or so on that front.  Also, if you look at the Accellera membership roster you'll notice a new name has appeared - that's right, Verilab is now a member!  I called into my first Accellera meeting last week - the Verification IP Technical Subcommittee meeting.  No major drama... yet :-).

Stay tuned...

Don't Worry, I Won't Quit My Day Job

Sorry, just couldn't resist the urge to show off my drawing skills courtesy of OneNote 2007 and a Lenovo X61 Tablet PC.

Looking Forward to 2008

I was looking through my web stats the other day when I noticed something strange - I was getting referrals from the DAC homepage.  A quick glance at the site revealed that Cool Verification is listed as one of several "industry blogs."  Here's the complete list from the DAC site:

• Adventures in ASIC
• ASIC-SoC-VLSI Design
• Cool Verification
• Deep Chip
• EDA Blog
• EDA Confidential
• Eric's Blog for Work
• Gabe on EDA
• John's Semi-Blog

This is the first time I've seen the DAC site mention blogs.  A closer look reveals they've also added a discussion of blogging to the press credential requirements. 

Last year when I attended DAC I managed to meet up with John Ford, author of DFT Digest.  Perhaps this year I'll get a chance to meet some of the other folks who blog on the topic of EDA.

Writing this article got me thinking that it's just about conference season again.  First up February 19-21 is DVCon in San Jose.  Following soon thereafter is DATE in Munich March 10-14.  SNUG in San Jose, CDNLive in Munich and DAC will carry us out through the middle of the year. 

This should be an interesting year.  We're all still anxiously waiting for the release of the OVM library (shh, don't tell anyone) from Cadence and Mentor.  It's also a year that (in my opinion) will start to see an even broader adoption of SystemVerilog, and perhaps some surprises from Synopsys as well. 

Comments on Cooley's Verification Census

Last month John Cooley released the results of his 2007 Verification Census.  He concluded, among other things, that SystemVerilog use is up, 'e' use is down, and that most engineers think specialty languages such as 'e' and Vera will be dead in 5 years.  Mike Fister, head honcho at Cadence shot back at Cooley saying that he felt the survey wasn't "statistically relevant".  Cooley claims his 818 responses must be significant, and that Fister is simply "protecting his $4 M paycheck":

My second question was "what is this 3% that Fister is talking about?"  Then
I figured 818 responses / 25,000 ESNUG subscribers = 3.2%.  That must be it.

Hmmm...  I'm not a statistician.  So I phoned Gary Smith about this 3%.

   "Heck, 818 responses is plenty.  We do directed surveys all the
    time and easily as few as 35 responses in a selected category can
    be statistically significant.  Fister needs to track these
    subcategories very closely to know.  So far, Cadence has not been
    open at all about outside information coming into the company."

        - Gary Smith of Gary Smith EDA

OK, so I'm not drinking my own Kool-Aid in this survey.  Crap!  And I'm just
now remembering all those CNN polls where they only asked *500* people about
some Big Issue -- and *that* poll data is considered statistically kosher
to represent the attitudes of 300 million Americans!  Crap.

All this barking was just Mike Fister protecting his $4 M paycheck.  Funny.

After reading this exchange, I felt as though both Cooley and Fister had made mistakes regarding the validity of survey data. I am definitely not a survey expert, so I decided to do some checking on the web to find out whether any of the claims regarding the veracity of Cooley's data could be true.

SVUG and DVClub - March 20, 21, and 22

Here's a quick heads up for all you verification gurus and guru wannabes out there - this week both DVClub and SVUG will be holding events in Austin.  DVClub is being held this Wednesday, March 21 in the usual location, and will address practical implications of utilizing formal verification methodologies. 

SVUG is being held at Cool River Cafe starting at 2pm this Thursday, March 22.  SVUG will also be holding an event in San Jose earlier in the week on Tuesday, March 20 at the Smoke Tiki Lounge.  Verilab's very own Jason Sprott, our VP of Consulting, will be presenting on how to create and manage functional coverage metrics in SystemVerilog.  It looks like Cliff Cummings from Sunburst Design and Hans van der Schoot from XtremeEDA will also be presenting.

I'll be at both of the Austin events.  I look forward to seeing some of you there!

Fitzpatrick on SystemVerilog

Last week I quoted Tom Fitzpatrick, Verification Technologist at Mentor Graphics as saying "SystemC and SystemVerilog are the only two growing verification standards", and that e and Vera were on the decline.  Mike Stellfox from Cadence Design Systems disagreed, and provided an analysis of the situation from his perspective.  I asked Tom if he had a rebuttal to Mike's response, and yesterday he provided one.  Here's what Tom had to say:

Intel@UT: “Hundreds of Cores: Verification Challenges of Tera-scale Computers”

Earlier this week I attended a presentation hosted by the Computer Engineering Research Center at The University of Texas at Austin and given by Brian Moore, Director of Validation Research in Intel's Microprocessor Technology Lab.  In "Hundreds of Cores: Verification Challenges of Tera-scale Computers" (sorry, haven't been able to find a link to the actual slides yet), Moore discussed recent advances in computer architecture and the challenges that validation teams will face as a result.  I was hoping he would delve into detail about the types of tools and techniques Intel was using to validate multi-core processors, and what his views were on whether those technologies would scale.  Instead, the discussion was more general, perhaps more focused on motivating the students in attendance.  Below, I'll summarize the talk and provide observations on where I would have liked to have learned more. 

Interviewing with Verilab

Verilab is hiring in the US and Europe.  We're looking for folks who are passionate about verification and are interested in learning new things.  Desire to travel is also a big plus.  If you've ever wondered what type of questions you might encounter in a Verilab interview check out Avidan's description over on Specman Verification.  If someone from Verilab asks you those questions in your interview there's now little excuse to get them wrong!

Hardware Verification with C++

Back in October, I received a mail from Mike Mintz asking if I'd like to take a look at a book he just wrote with Robert Ekendahl - "Hardware Verification with C++, A Practitioner's Handbook".  It sounded interesting enough, and I knew Mike had been working on a C++ verification library from a brief correspondence we had about a year ago, so I agreed to give it a read.  Around the same time, I read a post by Joel Spolsky (Book Review: Beyond Java) where he reviews a recent book by Bruce Tate (Beyond Java).  As luck would have it, at the same time all of this was going on I also had just upgraded to an unlimited subscription for O'Reilly's Safari Books Online, which meant I could immediately start reading "Beyond Java" (which I did).  Reading these three items got me thinking about the state of the art programming-wise in hardware verification versus state of the art in the software industry as a whole.

Large-Scale Hardware Simulation: Modeling and Verification Strategies

I received a link to the paper "Large-Scale Hardware Simulation: Modeling and Verification Strategies" from a colleague last month, but just got around to reading it today.  It's an interesting analysis of verification strategies written by Douglas Clark from DEC back in 1990.  In the paper, Doug discusses the importance of using bug rate instead of checking boxes off of a test plan as the determining factor for when verification is complete.  He also discusses the importance of random verification, the benefits of simulating the real design instead of a model, and the value of doing everything possible to trade engineering time for CPU cycles. 

The thing that strikes me the most about this paper is that it is still relevent, even after 16 years.  The other thing about the paper that I find interesting is that some people feel directed testing is fine for the small designs of today.  If you think about it, the large designs in 1990 were potentially even smaller than the small designs of today.  Anyways, take a look at the paper and let me know what you think!