Cool Verification

SystemVerilog 2012, DVCon 2010, and Travel

Now that the SystemVerilog 2009 standard has been released, the P1800 working group is getting ready to start work on the next version of the SystemVerilog standard.  As part of that effort, they are soliciting feedback in preparation for an open meeting on February 26 (the Friday after DVCon) where new features will be discussed (see also Brad Pierce's blog article on the topic).  Since you'll already be at DVCon (you ARE going to DVCon, right?), it should be easy to take the time to attend the IEEE meeting the next day.  Having said that, I'm going to miss the meeting as I'll be on my way to Shanghai to kick off a week of workshops in Asia, but one of my colleagues from Verilab may be attending.  

Speaking of DVCon, the early registration deadline is fast approaching.  Full conference registration is $485 before January 29.  After that, registration goes up to $565. The conference should be outstanding this year, despite the fact that I will be more actively involved than ever before ;-).  If you're planning to attend, please stop by and say hello at one of the following events:

• Monday Tutorial: Advanced Verification Techniques Using VMM - I'll be presenting for 45 minutes on the new phasing and factory features in the VMM 1.2.
• Wednesday Industry Leader's Panel: "What Keeps You Up At Night?" (2010-02-17 - I'm moderating this panel - check out my recent post What Keeps You Up at Night for details)
• Thursday session 12.1: Stimulating Scenarios in the OVM and VMM - My favorite methodology topic now as a DVCon paper with my coauthor Scott Roland.
• Thursday Panel: Ever-Onward! Minimizing Verification Time and Effort - Somehow I managed to sneak onto this panel with this distinguished group of panelists. Come by and heckle me for a bit while the votes for best paper are calculated.

As a side note, I'll be traveling extensively in the next couple of months.  If you're located in any of the following cities, send me a note and perhaps we can catch up while I'm in town:

• Boston (this week!)
• Mountain View (next week)
• Irvine (next week)
• San Jose (for DVCon)
• Shanghai (first week of March)
• Taipei/Hsinchu
• Tokyo

Finally, if any of you are reading this and thinking - why isn't JL writing about something more interesting like, say, the UVM, please send me a note letting me know. I've had blog writer's block/burnout for the last few months and could use the encouragement ;-).

The Relevance of Formal Methods

In a fascinating (to me) twist of fate, I will be moderating a panel on the “next big thing” in formal methods at FMCAD 2009 in Austin, Texas. The panel, entitled “What will be the next breakthrough solutions in formal?” is being held from 11:50-14:00 on Wednesday, November 18, and is made up of four distinguished panelists:

• Harry Foster, Mentor Graphics
• Ziyad Hanna, Jasper Design Automation
• Kevin Harer, Synopsys
• Axel Scherer, Cadence

Those of you who have been reading Cool Verification for awhile will note that I have never really discussed the topic of formal methods on this blog.  Truth is, I’ve yet to come across a situation on a project where I needed to use formal to get the job done. My theory is that there are a couple of issues preventing wide-spread adoption of formal tools in a standard verification flow.  First, the impression I get is that using formal well requires special expertise to write appropriate properties, partition the design, and interpret the results of the tools.  Second, the fact that you need special tools at all. In other words, the fact that I need a separate tool in my flow other than Questasim, VCS, or IUS (not to mention a separate license) makes it difficult for someone to try out formal techniques outside the tool flow of a typical project.

During the panel I plan to ask panelists about just such issues, plus several other questions proposed by thoughtful engineers just like you on the Google Moderator site set up for just this purpose.  In fact, I’d like to request your assistance. If you have a question you’d like to see asked of one of the panelists please submit it (or vote on your favorites) via the Google Moderator site or by mailing me directly at jl at coolverification dot com. 

I’m also quite interested to hear any stories readers may have with respect to the adoption (or lack thereof) of formal tools in your respective companies and current projects.  There are several types of formal tools out there… Any types of tools you’ve had great success with in particular? Or great failures? Does the choice of formal technique heavily depend on the application domain in question? What do you think the EDA vendors need to address in tool functionality/usability in order for you to consider adopting formal more broadly?

And of course, if you’re planning on being in Austin for FMCAD please let me know!

Do You Know Your Project's 'Truck Factor'?

Yesterday I presented another full-day workshop on verification planning - this time in Denver. During these workshops I discuss two major topics. First, we discuss a framework to help you understand your design. We break up a design into "efficient" subsections, and then search for "operations" that make up each of these subsections. Second, once you have an understanding of your design, we discuss the concept of a Failure Mode and Effects Analysis (FMEA). An FMEA is a cross-functional meeting used to brainstorm possible faults and failures. We use that information to come up with a verification plan.

Cool Demo – Low Power Sims with CPF, Incisive and SimVision

My good friends at Cadence have been gently pinging me for awhile trying to convince me to write about some of their more interesting verification-related announcements.  Unfortunately, I’m always in the middle of client work and somehow never get around to putting pen to paper (for example, I missed out on the recent and unfortunately timed announcement about Cadence’s recent IP acquisition).  However, Mickey Rodriguez’s recent blog post and associated video demonstrating how to use CPF with Incisive caught my attention. 

The video is not too long (about 8 minutes) and shows how to create a CPF file describing power characteristics of a simple design module.  It then shows how signal outputs affected by power domains look in the SimVision waveform and schematic viewer.  The text in the video was difficult to read on my 1024x768 display, but hopefully it will look better in full screen mode on a larger display.  Check it out!

DAC, Accellera and Web 2.0

It's been awhile but don't worry, I'm still here!  If you'd like to see what I'm up to in real-time feel free to check out my Twitter feed (also from the Cool Verification homepage).  I'm testing out Twitter (and some other new web apps such as Jott and Remember the Milk) in preparation for DAC and apparently as a way to convince myself and my wife (ok, just my wife) that I need an iPhone.  I've also got some cool things to announce about Verilab and our activities at DAC this year - look for more in the next week or so on that front.  Also, if you look at the Accellera membership roster you'll notice a new name has appeared - that's right, Verilab is now a member!  I called into my first Accellera meeting last week - the Verification IP Technical Subcommittee meeting.  No major drama... yet :-).

Stay tuned...

Don't Worry, I Won't Quit My Day Job

Sorry, just couldn't resist the urge to show off my drawing skills courtesy of OneNote 2007 and a Lenovo X61 Tablet PC.

Looking Forward to 2008

I was looking through my web stats the other day when I noticed something strange - I was getting referrals from the DAC homepage.  A quick glance at the site revealed that Cool Verification is listed as one of several "industry blogs."  Here's the complete list from the DAC site:

• Adventures in ASIC
• ASIC-SoC-VLSI Design
• Cool Verification
• Deep Chip
• EDA Blog
• EDA Confidential
• Eric's Blog for Work
• Gabe on EDA
• John's Semi-Blog

This is the first time I've seen the DAC site mention blogs.  A closer look reveals they've also added a discussion of blogging to the press credential requirements. 

Last year when I attended DAC I managed to meet up with John Ford, author of DFT Digest.  Perhaps this year I'll get a chance to meet some of the other folks who blog on the topic of EDA.

Writing this article got me thinking that it's just about conference season again.  First up February 19-21 is DVCon in San Jose.  Following soon thereafter is DATE in Munich March 10-14.  SNUG in San Jose, CDNLive in Munich and DAC will carry us out through the middle of the year. 

This should be an interesting year.  We're all still anxiously waiting for the release of the OVM library (shh, don't tell anyone) from Cadence and Mentor.  It's also a year that (in my opinion) will start to see an even broader adoption of SystemVerilog, and perhaps some surprises from Synopsys as well. 

Comments on Cooley's Verification Census

Last month John Cooley released the results of his 2007 Verification Census.  He concluded, among other things, that SystemVerilog use is up, 'e' use is down, and that most engineers think specialty languages such as 'e' and Vera will be dead in 5 years.  Mike Fister, head honcho at Cadence shot back at Cooley saying that he felt the survey wasn't "statistically relevant".  Cooley claims his 818 responses must be significant, and that Fister is simply "protecting his $4 M paycheck":

My second question was "what is this 3% that Fister is talking about?"  Then
I figured 818 responses / 25,000 ESNUG subscribers = 3.2%.  That must be it.

Hmmm...  I'm not a statistician.  So I phoned Gary Smith about this 3%.

   "Heck, 818 responses is plenty.  We do directed surveys all the
    time and easily as few as 35 responses in a selected category can
    be statistically significant.  Fister needs to track these
    subcategories very closely to know.  So far, Cadence has not been
    open at all about outside information coming into the company."

        - Gary Smith of Gary Smith EDA

OK, so I'm not drinking my own Kool-Aid in this survey.  Crap!  And I'm just
now remembering all those CNN polls where they only asked *500* people about
some Big Issue -- and *that* poll data is considered statistically kosher
to represent the attitudes of 300 million Americans!  Crap.

All this barking was just Mike Fister protecting his $4 M paycheck.  Funny.

After reading this exchange, I felt as though both Cooley and Fister had made mistakes regarding the validity of survey data. I am definitely not a survey expert, so I decided to do some checking on the web to find out whether any of the claims regarding the veracity of Cooley's data could be true.

SVUG and DVClub - March 20, 21, and 22

Here's a quick heads up for all you verification gurus and guru wannabes out there - this week both DVClub and SVUG will be holding events in Austin.  DVClub is being held this Wednesday, March 21 in the usual location, and will address practical implications of utilizing formal verification methodologies. 

SVUG is being held at Cool River Cafe starting at 2pm this Thursday, March 22.  SVUG will also be holding an event in San Jose earlier in the week on Tuesday, March 20 at the Smoke Tiki Lounge.  Verilab's very own Jason Sprott, our VP of Consulting, will be presenting on how to create and manage functional coverage metrics in SystemVerilog.  It looks like Cliff Cummings from Sunburst Design and Hans van der Schoot from XtremeEDA will also be presenting.

I'll be at both of the Austin events.  I look forward to seeing some of you there!

Fitzpatrick on SystemVerilog

Last week I quoted Tom Fitzpatrick, Verification Technologist at Mentor Graphics as saying "SystemC and SystemVerilog are the only two growing verification standards", and that e and Vera were on the decline.  Mike Stellfox from Cadence Design Systems disagreed, and provided an analysis of the situation from his perspective.  I asked Tom if he had a rebuttal to Mike's response, and yesterday he provided one.  Here's what Tom had to say: