Just in case you missed it, Cliff and Kevin had an interesting exchange in the comments to Kevin's original article on potential flaws in Cliff's FIFO2 SNUG paper. I'd encourage everyone to check it out if you haven't already!
December 11, 2006 Update: Check out the response from Cliff and additional info from Kevin in the comments section of this post.
Editor's Note: Today special guest Kevin Johnston from Verilab will be joining us to provide an analysis of FIFO designs published by Cliff Cummings for SNUG 2002. Prior to joining Verilab as a consultant in 2005, Kevin spent 14 years at Motorola/Freescale working on a variety of processor and SoC designs including the PowerPC and 68k. The following article is his first post on Cool Verification. Hope you enjoy it! -- JL.
There are two basic async FIFO design styles:
"Pointer-less", also known as "fall-through" type:
Fully-asynchronous, self-timed control logic (full-custom or compiled,
embedded in the data memory array design) autonomously clocks write
data from any current memory location to the subsequent memory location
if that subsequent location is empty; the data "falls through" the FIFO
from the memory cells connected to the Write port to the memory cells
connected to the Read port.
"Pointer based": The data array is a standard dual-port SRAM
block; all control logic is external to the memory. A Write Pointer
supplies the array address on the Write port, and a separate Read
Pointer supplies the array address on the Read port. The data remains
in the same memory location for the duration of its residence in the
FIFO; the Write Pointer and Read Pointer cycle through the memory
address range in identical sequences to retrieve the data in the same
order it was entered.