Cool Verification

What Keeps You Up at Night?

For those of you who have not been paying attention, DVCon 2010 starts next week. In a previous post I described several events I'll be involved with except for one very important item.  This year I will be moderating the newly dubbed Industry Leaders Panel right after Lip-Bu Tan's keynote address.  The panel starts at 3:30pm on Wednesday, February 24.

Why am I hosting the panel this year? As it turns out, David Letterman, John Stewart, and Hugh Jackman were not available (click the link then scroll down and watch the video), so the DVCon steering committee was stuck with me ;-).

This year’s panel will ask the panelists “What Keeps You Up At Night?” and other pressing questions about what they see as the market’s challenges and opportunities. There will, as usual, be a no-holds-barred question and answer period. The panel will be made up of senior managers and directors from some of the world's top semiconductor companies (large, medium, and small), along with the analyst and consultant perspectives.

• Steven Gary - Numetrics Management Systems, Inc.
• John Goodenough - ARM Ltd.
• Sheela Pillai - Advanced Micro Devices, Inc.
• Jim Crocker - Paradigm Works, Inc.
• Victor Melamed - Ambarella

I would very much appreciate and enjoy any public or private comments you would like to share with me about what keeps you up at night on the types of projects you work on. I'm sure those of you approaching tapeout will have a long list! Also, I would like to make the panel as interactive as possible, and will collect any questions you'd like me to ask the panelists on your behalf. Feel free to post comments to this post or mail me at jl at coolverification dot com.

Thanks all, and I look forward to seeing you at DVCon next week!

SystemVerilog 2012, DVCon 2010, and Travel

Now that the SystemVerilog 2009 standard has been released, the P1800 working group is getting ready to start work on the next version of the SystemVerilog standard.  As part of that effort, they are soliciting feedback in preparation for an open meeting on February 26 (the Friday after DVCon) where new features will be discussed (see also Brad Pierce's blog article on the topic).  Since you'll already be at DVCon (you ARE going to DVCon, right?), it should be easy to take the time to attend the IEEE meeting the next day.  Having said that, I'm going to miss the meeting as I'll be on my way to Shanghai to kick off a week of workshops in Asia, but one of my colleagues from Verilab may be attending.  

Speaking of DVCon, the early registration deadline is fast approaching.  Full conference registration is $485 before January 29.  After that, registration goes up to $565. The conference should be outstanding this year, despite the fact that I will be more actively involved than ever before ;-).  If you're planning to attend, please stop by and say hello at one of the following events:

• Monday Tutorial: Advanced Verification Techniques Using VMM - I'll be presenting for 45 minutes on the new phasing and factory features in the VMM 1.2.
• Wednesday Industry Leader's Panel: "What Keeps You Up At Night?" (2010-02-17 - I'm moderating this panel - check out my recent post What Keeps You Up at Night for details)
• Thursday session 12.1: Stimulating Scenarios in the OVM and VMM - My favorite methodology topic now as a DVCon paper with my coauthor Scott Roland.
• Thursday Panel: Ever-Onward! Minimizing Verification Time and Effort - Somehow I managed to sneak onto this panel with this distinguished group of panelists. Come by and heckle me for a bit while the votes for best paper are calculated.

As a side note, I'll be traveling extensively in the next couple of months.  If you're located in any of the following cities, send me a note and perhaps we can catch up while I'm in town:

• Boston (this week!)
• Mountain View (next week)
• Irvine (next week)
• San Jose (for DVCon)
• Shanghai (first week of March)
• Taipei/Hsinchu
• Tokyo

Finally, if any of you are reading this and thinking - why isn't JL writing about something more interesting like, say, the UVM, please send me a note letting me know. I've had blog writer's block/burnout for the last few months and could use the encouragement ;-).

The Relevance of Formal Methods

In a fascinating (to me) twist of fate, I will be moderating a panel on the “next big thing” in formal methods at FMCAD 2009 in Austin, Texas. The panel, entitled “What will be the next breakthrough solutions in formal?” is being held from 11:50-14:00 on Wednesday, November 18, and is made up of four distinguished panelists:

• Harry Foster, Mentor Graphics
• Ziyad Hanna, Jasper Design Automation
• Kevin Harer, Synopsys
• Axel Scherer, Cadence

Those of you who have been reading Cool Verification for awhile will note that I have never really discussed the topic of formal methods on this blog.  Truth is, I’ve yet to come across a situation on a project where I needed to use formal to get the job done. My theory is that there are a couple of issues preventing wide-spread adoption of formal tools in a standard verification flow.  First, the impression I get is that using formal well requires special expertise to write appropriate properties, partition the design, and interpret the results of the tools.  Second, the fact that you need special tools at all. In other words, the fact that I need a separate tool in my flow other than Questasim, VCS, or IUS (not to mention a separate license) makes it difficult for someone to try out formal techniques outside the tool flow of a typical project.

During the panel I plan to ask panelists about just such issues, plus several other questions proposed by thoughtful engineers just like you on the Google Moderator site set up for just this purpose.  In fact, I’d like to request your assistance. If you have a question you’d like to see asked of one of the panelists please submit it (or vote on your favorites) via the Google Moderator site or by mailing me directly at jl at coolverification dot com. 

I’m also quite interested to hear any stories readers may have with respect to the adoption (or lack thereof) of formal tools in your respective companies and current projects.  There are several types of formal tools out there… Any types of tools you’ve had great success with in particular? Or great failures? Does the choice of formal technique heavily depend on the application domain in question? What do you think the EDA vendors need to address in tool functionality/usability in order for you to consider adopting formal more broadly?

And of course, if you’re planning on being in Austin for FMCAD please let me know!

The Past, Present and Future of the Design Automation Conference

It’s over. After weeks of preparation (on my part, a year on the part of countless others), and a week of staying up late then getting up early, the 46th Annual Design Automation Conference has finally come to a close.  One of the main highlights of the conference was the Synopsys-hosted Conversation Central interactive forum on social media.   I also enjoyed my opportunity to participate on a Pavilion Panel on “Seeking the Holy Grail of Verification Coverage Closure”, to present the new VMM 1.2 updates in the Synopsys theater, and to give a presentation entitled “Zero to Sequences in 30 Minutes” in the OVM World booth.  Special thanks to all of you who spent time talking with me on Monday and Tuesday sharing your thoughts with me on that topic to help me prepare for the panel.  And of course, there was the ever-enjoyable Denali Party (click here for pictures)!

Throughout the conference though, I had a nagging suspicion that I was missing some perspective on where we’ve been as an EDA industry, where we are currently, and where we’re going in the future.  This being only my third DAC, it wasn’t clear to me if anyone was around from the earlier days who would be able to help me fill a gap in my industry knowledge.  After asking around, I quickly realized that I needed to speak with Marie and Pat Pistilli, founders of the aptly named MP Associates and organizers of the very first DAC back in 1964 (and every DAC since).  At the time, DAC was, according to Pat actually called SHARE, which stood for the “Society to Help Avoid Redundant Effort”. 

Pat Pistilli, MP Associates

I was able to arrange a time to meet with Pat on Wednesday evening before the DAC party.  I wasn’t really sure what to expect, and Google wasn’t much help.  So naturally, I asked Pat to tell me about his background and how he ended up founding DAC. In the late 50s Pat was working at Bell Laboratories on a project called “Safeguard”.  (For info on Safeguard, check out the ever-useful Wikipedia. Also, this site dedicated to the Mickelson Safeguard Complex contains a list of references that appear to be relevant).  The idea of the project was to create a computer that could quickly identify which Soviet ICBMs were duds and which were real during a nuclear attack.

SNUG Plug: Multi-Stream Scenarios and the VMM

Ok, I know what you’re all thinking… “JL, you haven’t even finished writing up DVCon yet and now you’re talking about SNUG?!” Yes, I know.  Let’s just say an annoying stream of illnesses have taken their toll on the Gray family (and many other folks as best as I can tell) over the last few weeks.  But things seem almost back to normal now and I didn’t want to miss out on an opportunity to let everyone know about my official debut as a conference paper presenter at SNUG San Jose next week. 

My Verilab colleagues Jason Sprott and Sumit Dhamanwala, along with Cliff Cummings from Sunburst Design and yours truly authored a paper entitled “Using the New Features in VMM 1.1 for Multi-Stream Scenarios”. I’ll be presenting the paper during session MA4: Verification with VMM I on Monday at 11am.  Those of you who attended one of the Verification Now 2008 seminars back in the fall will recognize the topic. I discussed the yet to be announced Multi-Stream Scenario additions to the VMM in one of my presentations. 

Unlike my Verification Now presentation which compared stimulus in the OVM to the VMM, the SNUG presentation will delve into the topic of Multi-Stream Scenarios in the VMM in more detail.  Specifically, I will review the following topics:

• Recap: Single Stream Scenarios
• Complex Stimulus with Multi-Stream Scenarios
• Multi-Stream Scenario Registries (Channel, MSS, and MSSG)
• Single Stream vs. Multi-Stream Scenarios
• Resource Sharing: Grab/Ungrab
• Multi-channel grab

One of the things I hope to touch on is the importance of using the registries when building multi-stream scenarios instead of directly instantiating sub-scenarios, channels, or scenarios from other multi-stream scenario generators (using the generator registry).  Those features were added to the MSS solution to allow integrators and test writers to modify the behavior of specific scenarios and scenario generators without having to modify the underlying scenarios themselves. 

Another goal is simply to promote the topic of reusable, multi-stream stimulus itself. The VMM has historically supported a flat testbench structure. New features such as MSS, when combined with the vmm_subenv should lead to more reusable and maintainable testbenches.

I’m thrilled to have an opportunity to present at SNUG this year and to meet readers of this blog and my Twitter feed.  I will be twittering SNUG using the hash tag #snug, unless someone gives me a good reason to use a different tag.  Of course, that begs the question – who will twitter my presentation while I’m presenting?  How about this… I will buy the person who Twitters the most insightful comments and/or questions during my presentation a delicious beverage of his/her choice. Any takers?

DVCon 2009 Wrap Up: Attendance

DVCon, the first big verification-related conference of the year is now complete. Unlike in past years where I’ve spent quite a bit of time during the conference blogging about what’s been going on each day, I’ve decided this year (as you may have noticed) to do a series of wrap up articles instead.  Why?  One big reason is that I was able to describe many of the minute by minute details of the conference on Twitter along with many of my new EDA Twitter friends.  More on that in a future post (or check out Karen Bartleson’s post on her Twitter experience at DVCon). Another reason is that I wanted to spend more time taking in the conference itself as opposed to huddled in a corner somewhere writing up blog articles. If you have any preferences for one over the other please let me know so I can make adjustments if necessary at DAC.

In this post I’m going to discuss conference attendance. Stay tuned for upcoming posts on Formal vs. Dynamic Simulation, industry moves towards improving constrained-random simulation, my theory that SpringSoft should eventually buy Jasper, the Wednesday “EDA: Dead or Alive” panel, and the use of Twitter at #dvcon.

DVCon 2009: Coming Soon to a Theater Near You!

It’s that time of the year again – DVCon starts this Tuesday, February 24 in San Jose.  First off, here is the list of sessions I’m tentatively planning on attending.

Tuesday

• Accellera Technical Committee Luncheon
• I’m skipping the tutorials on Tuesday as I’m not arriving in SJC until Tuesday morning and I’ve got meetings scheduled all afternoon.

Wednesday

• Prototyping: Where Hardware and Software First Meet
• Verification Methodology and Testbenches – I
• Increasing Functional Coverage
• Case Studies of OVM in Multi-language Verification Environments
• Keynote: The Techonomics of Verification
• EDA: Dead or Alive? (The old Troublemakers Panel slot, now hosted by Peggy Aycinena)
• SaaS and Cloud Computing EDA Roundtable

Thursday

• Verification Data Management
• Case Studies – I
• Risky Business: How Do I Manage Risk in My Next Design Project?
• Case Studies – II
• Mixing Formal Analysis with Simulation: Why, When, Where, and How?

Note: If you’ve registered for the conference you can create your own custom downloadable schedule on the DVCon Zerista website.  The Zerista site is new this year and, in addition to creating a custom schedule allows registrants to network with other conference attendees.  It’s a great idea (if I do say so myself) but I think the scheduling mechanism could use some significant work, especially if someone was planning on using it for DATE or DAC.

Next, do you have a Twitter account?  One of the cool things in the pipeline for DVCon this year is that many attendees have signed up for Twitter accounts and are planning on twittering throughout the conference.  You can follow my activities at DVCon via my personal Twitter feed. Don’t understand Twitter?  Here’s a great video describing what Twitter is and why you might want to use it: Twitter in Plain English (thanks, Tommy!). 

The first year I blogged at DVCon (back in 2007) I spent a lot of time writing about each and every thing I did during the conference.  Last year I toned it down a bit, but this year I’m definitely going to focus my attention on one or two topics, as the nitty-gritty details will all be on Twitter. 

What else… oh, it looks like I’m going to have some company on the bloggers-as-press front (sorry Peggy).  Harry “The ASIC Guy” Gries will be attending the conference and will be blogging about his experiences over on his site.  Harry is also organizing the SaaS and Cloud Computing EDA Roundtable I mentioned above.  Harry is a great guy and I expect to see some interesting material from him over the next week or two about the conference.

Overall, I’m most excited this year to meet up with friends and colleagues, both old and new.  I’m also hoping to learn more about how the VMM and OVM are being used on real projects and whether users are looking for new features to be added (including features related to interoperability).

What are you interested in learning from DVCon (especially those of you not attending)?  I’ll be happy to do some digging around if anyone has any requests!

DVCon Misfits Unite!

DVCon starts three weeks from today.  Back in December, Brian Bailey commented that the DVCon program has too much of a focus on vendor-generated content.  I know for my part I was too busy back in August to spend the time to submit a paper abstract, even though at the time I already had an abstract and was developing slides for a perfectly good presentation on stimulus generation in the VMM and OVM.  Since then I've continued my involvement with the Accellera VIP TSC and executed on a couple of customer engagements.  

VMM - Robust and Open, Stale and Proprietary or Somewhere In Between?

Last week I wrote an article about what appears to be an upcoming standards battle pitting the OVM vs. the VMM.  My comments seem to have touched a nerve with a large number of people and prompted comments from Janick Bergeron of Synopsys, Dennis Brophy of Mentor and Ambar Sarkar of Paradigm Works, among others.  Since this thread is starting to take the form of an all out smack-down, I figured perhaps the readers of this site could help me pick out appropriate avatars for Janick, Ambar, Dennis, and myself.  Figured out who's who?   Good, now let's continue!

Janick was concerned that my argument contained some factual errors - specifically with my assertions that:

1. The VMM is not open.
2. The VMM is not as feature-rich as the OVM. 

Ambar commented on the need for an open reference implementation of any potential standard verification methodology library.  He also bemoaned the lack of support for the SystemVerilog standard among the EDA vendors, and ended with a comment that the verification community "may not have the stamina or patience for morphing VMM/OVM into yet another methodology." 

Finally, Dennis challenged Synopsys to "post their customer & partner license terms and conditions," the implication being that Synopsys uses restrictive licensing agreements with its customers. 

Comments on "The Brewing Standards War"

Updated 2/25/2008: Fixed a typo.

I wanted to let everyone know there have been some interesting and important comments to my post on "The Brewing Standards War", including one from Janick Bergeron of Synopsys and one from Ambar Sarkar of Paradigm Works.  I just got back to Austin and hope to respond to the comments within the next day or two once I get a chance to recover from my trip.  In the meantime, please feel free to add your own thoughts if you'd like to add to the discussion!