One of my main goals during my trip to CDNLive! in San Jose a couple of weeks ago was to find out more about the Mentor/Cadence OVM SystemVerilog library. I spoke with several folks from Cadence, and also pinged someone from Mentor Graphics who was attending the EDA Tech Forum over in Santa Clara. The big question in my mind has been trying to understand how the AVM and URM were going to be merged together into a common library that would remain compatible with legacy environments.
This afternoon, the Most Valuable Paper award at CDNLive! San Jose was given to conference junkie  Kelly Larson from Analog Devices in Austin, Texas for his paper entitled "Translation of an Existing VMM-Based SystemVerilog Testbench to URM". I sat in on Kelly's presentation and agree with the conference organizers that it was an outstanding analysis of the differences between VMM and URM, and would be a big help for anyone transitioning between the two environments. As a Specman user now working on a VMM testbench, I also found it helpful in demonstrating how to map the eRM concepts I'm used to in e into a SystemVerilog/VMM environment. Congrats Kelly!
 - For those of you who don't know Kelly, he's presented at several US conferences this year!
Yesterday morning I attended the opening keynote session. Michael Catrambone, chairman of the CDNLive! Steering Committee kicked things off, followed by Mike Fister, Cadence CEO, and Alterto Sangiovanni-Vincentelli, a professor at UC Berkeley and member of the board of Cadence. Mike Santarini over at EDN wrote up an excellent summary of Fister's talk and shared his thoughts on Fister's improved public speaking skills. I'm glad Mike took so much useful info away from the keynote, because most of the time I found myself staring blankly at the stage and video screens as Fister described manufacturing, complexity, and scale challenges that focused largely on the back-end of the design process. I snapped back to attention when the topic of advanced verification came up. The OVM was prominently mentioned as a means of delivering SystemVerilog interoperability between vendors and accelerating SV adoption. Fister also pointed out that the OVM would provide a framework to create verification IP.
Before I go, I'd like to mention that as usual, my coverage of this conference is brought to you by my employer, Verilab, letter 'v', and the numbers 4, 5, and 6. I'd also like to mention a few other things. First, Verilab is hiring in the US, UK, and Germany. Second, I'll be giving away copies of David Robinson's new book, Aspect Oriented Programming and the e Verification Language this week at the Cadence verification partners booth. I haven't yet decided how I'm going to give the books away. If anyone has suggestions let me know. Third, if you happen to be in San Jose this week, drop me a line! I'm always interested in meeting Cool Verification readers and folks who want more information about working with/for Verilab.
I arrived in San Jose earlier this evening after spending the day yesterday in Seattle. The convention center was bustling as Cadence and the conference support staff get ready for CDNLive! to start tomorrow. Strictly speaking, it's already started, as there were "techtorials" all day today. Not having anything better to do, I decided to wander around the convention center to see if I could find someone from Cadence to chat with to see how the conference prep was going. Only problem was, I didn't feel like changing out of my grimy travel clothes (shorts and a T-shirt), or bringing a notebook/camera with me. I mentioned this to my wife over the phone just before I went down to the convention center. We both agreed there was little chance of anyone caring, especially since I wasn't likely to meet anyone new...
For several years I somehow managed not to attend any conferences. Today, I'm getting ready to fly to San Jose (with a quick jump up to Seattle for the weekend) for conference number four - CDNLive!. The conference program looks interesting, and I'll get to staff part of the Cadence IPCM Partner booth on Tuesday evening. If it wasn't already obvious from the name of the conference, this requiredquestion from the online registration form pretty much sums up what I expect to learn this week:
Which company do you believe is best at delivering inventive solutions that enable you to achieve breakthrough results?
Uh... Cadence? :-). I hope to have the opportunity to meet those of you who plan to attend. As I mentioned earlier, I'll be at the Cadence IPCM Qualified Partners booth on Tuesday evening to answer questions about Verilab and to give away ~4-5 copies of David Robinson's excellent new book, Aspect Oriented Programming with the e Verification Language. Luckily for me, the book is travel friendly and I was able to fit a stack in my carry on luggage.