JL Gray is a Senior Architect at Cadence Design Systems. Before joining Cadence in 2013, JL was Vice President and General Manager, North America at Verilab, Inc. based in Austin, Texas. JL has consulted extensively in verification planning, methodology development, and project execution with a wide range of clients doing ASIC development in the US and Europe. JL has presented workshops on verification methodology and planning around the world. He has also implemented verification environments using all of the major e and SystemVerilog libraries (eRM, VMM, OVM, and UVM).
In addition to his consulting activities, JL was a member of the Accellera Verification IP Technical Subcommittee (UVM) from 2009-2013. He is also a past member of the DVCon Steering Committee. JL also worked extensively on the application of social media to the EDA industry as a means of fostering collaboration in the wider engineering community. JL is well known in EDA as the author of Cool Verification, a blog about hardware verification.
Prior to joining Verilab, JL was one of the first verification engineers at ServerEngines where he created a verification environment using SystemC. He also spent 5 years at Intel, where he developed verification environments and methodologies using Specman for 1G and 10G Ethernet controllers.
JL has a BSEE from Purdue University in West Lafayette, Indiana. He can be reached at jl dot gray at coolverification dot com.
If you are looking for information on JL's photography, check out Brilliant Hue Photography.