As many of you know, DVCon 2013 is next week in San Jose, CA. Verilab will be there in force, including at the UVM tutorial on Monday, poster and paper sessions, a lunch panel, and last, but not least, my 4th Industry Leaders panel, The Road to 1M Design Starts:
How many times have you seen a great idea for a new design effort crushed because the cost of creating it was too great given the probability of getting a good return on investment? It happens at both big companies and small. And, what about the potentially revolutionary ideas that are never even considered because an engineering team or individual would never imagine that a chip would be a possible solution?
Like it or not, developing complex semiconductors comes at an enormous cost. New design flows including use of ESL, Design and Verification IP, Emulation, FPGAs, and the like have all helped contain some of the expansive growth in complexity associated with these efforts. But, is that enough?
What would need to take place in the next 10 years to, on the one hand, reduce the barrier of entry for smaller teams and on the other, dramatically enhance the capabilities of large teams working on the toughest challenges?
The DVCon 2013 Industry Leaders panel will answer the question - what will it take to get to 1M design starts per year?
Panelists:
- Yervant Zorian, Fellow and Chief Architect - Synopsys, Inc.
- Ziv Binyamini,Corporate Vice President, Systems and Software Solutions - Cadence Design Systems, Inc.
- Sunil Shenoy, Corporate Vice President, General Manager, Visual and Parallel Computing Group - Intel Corp.
- John Costello, Vice President, IC Design - Altera Corp.
- Serge Leef, Vice President, New Ventures - Mentor Graphics Corp.
The panel will be held this coming Wednesday, February 27 from 3:30-4:30pm in the Oak/Fir Ballroom at the DoubleTree Hotel in San Jose, CA. I hope to see you there!
