Many companies I work with end up using some form of verification IP (VIP) to help speed up and improve the quality their verification effort. And most of these companies soon discover that the term "quality VIP" is an oxymoron. Engineers have grand expectations when trying to convince their management to invest in VIP. They want VIP that (in order of importance)...
- Is free of major bugs
- Is easy to integrate into an existing environment, and comes with initial vendor support for such integration
- Comes with clear documentation and working code examples showing typical and advanced use models
- Has an interface compatible with the testbench language and methodology library I'm using (SV/UVM/OVM/VMM, e/eRM, C/SystemC, etc, etc, etc)
- Makes it easy to write tests and debug simulations
- Comes with a pre-packaged set of tests, checkers, and assertions for the interface in question
- Does not significantly slow down simulations
- In some cases, that can be synthesized for use with emulators
- And, in a perfect world, provides full access to source code to make it possible to debug issues that inevitably come up
None of the above specifically require that the core of any VIP be written in any particular language. So vendors that focus on the fact that the core of their VIP is written in, for example, SystemVerilog, are really, in my view, missing the point. A specific VIP implementation may help vendors reach the goals above, but if goals are not met, especially items 1-6, the implementation choices made are irrelevant.
I've worked with several customers who have used VIP on their projects. And in almost every case, there were some significant issues with the VIP in question that caused significant (i.e. 1-6 months) of project delay. These issues spanned multiple vendors and multiple VIP implementation styles.
So the next time you're speaking with your vendor, don't be fooled by talk about VIP implementation styles. Ask them how they meet the requirements listed above.
Are there other characteristics you look for when evaluating VIP? Let me know in the comments below.
And check out Austin SNUG 2012 papers from Asif Jafri on Low Power Verification and Jonathan Bromley on de-mystifying SystemVerilog clocking block useage in the Resources -> Papers and Presentations section of the Verilab website.