The UVM User guide recommends that an agent is composed of a driver, monitor, and sequencer (UVM 1.1a User Guide pg 35):
But I am frequently amazed to find that there are a large number of verification engineers who insist that creating a monitor is often not useful. These engineers prefer to perform checking based directly on the stimulus generated in a test, sequence, or driver. Why should we waste time creating a monitor, they argue, when we have all the info we need right here in the driver?!
For the record, you should, under almost every circumstance, create a monitor that can be run in a completely passive fashion when creating an agent for a DUT interface. This is because as your verification effort progresses from block to full chip, you will often want to reuse checkers. And in the full chip, a checker must frequently be passive - it is observing what is going on inside the DUT without having any direct control. If you construct your testbench using checkers based on stimulus, you will eventually have to rewrite those checkers if you hope to use them in a full chip environment.
You were planning to reuse your checkers... right?
Want more info on writing testbench stimulus? Check out this paper on scenarios and sequences from DVCon 2010.