This marks my 5th year attending the Design Automation Conference. Unlike prior years where I've lugged around my camera and had a schedule of events to participate in, this year, I came with a relatively free slate. No hard plans, just a todo list (thank goodness for OmniFocus for iPad) and my walking shoes. I wanted to share a quick list of a couple of my highlights from Monday.
As usual, my first few hours at DAC involved me wandering the show floor catching up with all of my friends and colleagues that I only get to see in person at conferences. Included in that list were Harry Gries and James Colgan, who were kind (and patient) enough to give me demo of Xuropa's latest cloud offerings in the Synopsys Partner's booth. I've been struggling with the benefits of EDA in the cloud for a few years now, but have recently seen some good use of outsourcing one's EDA IT infrastructure. But the product Xuropa (and Synopsys - more later) is pushing is a bit different than what I've been used to up to this point.
The idea seems to be that users would start and stop instances of servers on the "cloud" on an as-needed basis. I'm more used to the data center model where a few servers are always at my beck and call 24x7, and I pay even if I may not be using them at any given time. While I was looking at the Xuropa solution as a possible complete replacement for a company's internal infrastructure, it appears it may be better suited to occasionally augmenting capacity due to the seeming (to me) conceptual complexity of the user interface involved in starting up servers for interactive use. I'm sure Harry and/or James will jump in and be happy to explain where I've got it wrong :-).
Much later in the day I spoke with Synopsys about the new VCS cloud, which I believe is based on a very similar infrastructure to what is used by Xuropa (in fact, I believe Synopsys and Xuropa are partners on some aspects of the Xuropa product). But the VCS cloud use model somehow made more sense to me. The idea is that you have your own farm of compute servers running VCS. But sometimes you want, say, an extra 10000 CPU hours to help slog through a large regression. So you compile your simulation on your own servers, and push that entire image up to the Cloud for execution on Amazon's massive server farm. You only pay for what you use, and critically, the price includes the required Synopsys licenses (unlike the Xuropa offering where licenses purchases are handled separately by you with your vendors).
Unfortunately, if you use tools or vendor IP other than what is provided by Synopsys, I would expect there would be some complications with setup. There could even be legal complications as I discovered recently when trying to use an outsourced data center to manage design IP from one vendor where another vendor who was on bad terms with the first vendor controlled access to the hosted solution. If you are running a pure Synopsys flow the VCS cloud could be worth a serious look. If you run with a mixed flow the Xuropa solution may have a better long-term potential.
Beyond the cloud discussions with Synopsys and Xuropa, I was able to make time for the enjoyable discussion between Steve Wozniak and Mike Cassidy of the San Jose Mercury News. Check out my Twitter stream for some after-the-fact-real-time commentary. There was a big crowd present for the session, though I left feeling that somehow all the questions posed felt bit rehearsed - like nothing was asked that Wozniak had not been asked in (probably many multiple) interviews before. I would have enjoyed something a bit more in-depth and focused on the particular problems faced by DAC attendees. That being said, kudos to the DAC organizing committee for bringing in a big name to liven up the keynote.
Next, I spent about 30-45 minutes speaking with Dave Murray, Joe Hee, and Tamas Olaszi over at the Duolog booth (#2931). Tamas gave me a great demo of Socrates Bitwise, a register management tool. For those of you not familiar, a big problem on almost every chip design I've ever worked on is managing register definitions from documentation, to RTL, to verification test bench, to software and beyond. Most companies write a set of scripts to manage this task, and most companies end up falling far short of creating an easy to use, robust solution. Though I haven't used the tool, Bitwise seems the closest to an ideal implementation to commercial or in-house tool I've seen. They have a robust set of import APIs and export templates that can be used to easily process your existing register data and output in a format that exactly matches what you have already been using in your design and verification flow. Even better, since Duolog works with a wide variety of companies they should, in theory, be able to steer you towards generated code that most closely aligns with industry best practices so you don't have to go through the trial and error process that most companies use. If you have registers in your design, and if you are involved in chip design you most certainly do, then you owe it to yourself to stop by the Duolog booth to take a look.