Cool Verification

DVCon 2011: What engineers don't know about making great products

Those of you who attended DVCon last year may recall my panel "What Keeps You Awake at Night?". In that panel (check out the great writeup by Richard Goering for details) we brought together expert panelists on the front lines of chip design and verification to address the greatest concerns facing product development. This year, were taking things a step further and asking the folks who are the driving force behind successful product development to share their insights as part of my panel, "Making Great Products Great".  The panel will be held on Wednesday, March 2 at 3:45pm at the DoubleTree Hotel in San Jose. The panel is free to the public. Attendance simply requires filling out the free "Exhibits Only" DVCon registration.

DVCon 2011 Starts with a Bang: UVM Tutorial

It's that time of year - DVCon 2011 starts today. This is the 5th year I've attended DVCon, and today I saw something I haven't seen in prior years - a packed double-size room full of engineers anxiously awaiting the start of the UVM Tutorial sponsored by Accellera. 

The tutorial will cover the basics of the UVM, the new UVM Phasing mechanism, TLM, Sequences and Configuration, and the new UVM Register Package. Phasing has changed significantly in the UVM 1.0 release, as have sequences, configuration, and the register package... well, let's just say if you're interested in using the UVM this tutorial will be a great way to get caught up on what's new since the OVM 2.1.1.

I'll be in San Jose through Wednesday evening and would love to meet those of you attending the conference. Please flag me down and say hello! You can also follow me on Twitter, or follow the Twitter stream for all DVCon attendees using the #dvcon hash tag.