Update June 18, 2008: For my comments on Cadence's proposed buyout of Mentor Graphics check out my post entitled Cadence Offers to Buy Mentor - A Verification Consultant's Perspective.
Earlier this week a few colleagues of mine passed along the news that Cadence Design Systems, Inc. (CDNS) and Mentor Graphics Corp (MENT) were teaming up to develop a common verification methodology called the "Open SystemVerilog Verification Methodology". Keeping with what appears to be a common trend when naming verification methodologies, the acronym will be OVM. (See my Verilab colleague Avidan Efody's take on the announcement).
Is it significant that there is no "SV" in the OVM? Perhaps this will be a methodology that eventually encompasses SystemC and e? Hard to say, since the one thing that was missing from the announcement was any detail about what the OVM contains. I'll be attending CDNLive! in San Jose September 10-12. If nothing else, I'm sure I'll be able to dig up some additional info on the announcement there.
I have to admit, I was a bit shocked at first. I find it hard to believe that Mentor and Cadence could find it in their respective hearts to work together on a project of this magnitude, especially after the Specman vs. SystemVerilog spat at DVCon earlier this year, not to mention the ongoing UPF vs. CPF debate. However, on second thought I realized that in order for any of the big EDA companies to follow through on the marketing hype that SV is a standard language with multi-vendor support they're going to have to standardize on the methodology component as well. In fact, I wouldn't be surprised if this standardization effort was pushed through by large customers who want to make sure their SV investments don't lock them into a single vendor, and by design/verification IP vendors who don't want to have to go to the trouble of developing to the least common denominator of SV features.
Another thing to consider is the relative strengths and weaknesses of the Cadence and Mentor flows. These days, Mentor is neck and neck, if not slightly ahead of Synopsys with their SystemVerilog support. They've also got the open source Advanced Verification Methodology (AVM). Cadence is still behind with their SV support, but they have by far the best verification methodology out there in the e Reuse Methodology (eRM). Of course, the eRM only works with Specman. Cadence has been working on the Universal Reuse Methodology (URM), but last time I checked (at DAC in June) the methodology was module based, with the class based approach not likely to be generally available until October at the earliest. So, Cadence has the best methodology but poor support for SystemVerilog. Mentor is strong in SV but could use help with the AVM (IMHO).
By putting their heads together, they may be attempting to chop the legs out from under Synopsys and the VMM. What do I mean by this? Back in June, I wrote that decisions regarding EDA tools weren't made by the end users at all, but by a VP in a fancy office somewhere who realizes he/she can save tens of millions of dollars by switching, say, from Synopsys to Cadence. If executed properly, the sales teams at Mentor and Cadence will be able to provide a great story about their flows being vendor independent, except for that crazy Synopsys who still has the proprietary, closed-source VMM. What comes around goes around, eh?
Of course, the OVM could be vaporware. Synopsys could open source the VMM. In the end, only time will tell if the OVM has what it takes to be the standard verification methodology.