Cool Verification

Verification in the Spotlight (or Hot Lights) of DAC

Today I’d like to welcome guest poster Andrew Kahng, General Chair of this year’s Design Automation Conference. I’ve already registered for DAC and am looking forward to an exciting conference. If you are planning on attending please let me know – I’d love to meet up with you in San Francisco! 

Also, as an important note – the early registration deadline is Monday, June 29 (that’s now!). Please register ASAP to get the early-bird discount.

JL

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DAC is a mere five weeks away and, if you check out the technical program (www.dac.com), you’ll see that there are a host of sessions dedicated to verification and test.

While verification is not my area of expertise, a fast skim through the program and specific sessions makes it’s clear to me and anyone in this industry that verification is an ongoing, critical and unmet challenge.

Yes, verification is once again in the spotlight of this year’s DAC as we try to wrestle this challenge. Perhaps the Pavilion panel on the exhibit floor scheduled for Wednesday at 2 p.m. best sums up what we’re facing with the title, “Seeking the Holy Grail of Verification Coverage Closure.” Leading verification experts, including JL Gray, host of this blog Cool Verification, will attempt to determine which solution will lead to the ultimate verification coverage. Another noted verification expert Brian Bailey will moderate what should be a lively and informative discussion.

In addition, you will find sessions on a broad range of verification and test topics too numerous to mention throughout the week –– 16 by my count. They will be held in the IC Design Central Partner Pavilion, the Exhibitor Forum and the User Track, as well as a special session.

Two tutorials are dedicated to the topic of verification. The first, “Post-Silicon Validation and Runtime Verification: Ensuring Correctness after First Silicon,” will review state-of-the-art methods for detecting and correcting bugs after the first few silicon prototypes of a design become available. It will be held Friday from 9 a.m. to 5 p.m. “Functional Verification Planning and Management: Navigating from Specification to Functional Closure” will also be held Friday from 9 a.m. to 5 p.m. Its instructors will present leading-edge methods for planning, monitoring and assessing verification progress. Both seem timely and topical.

Of course, the exhibit hall will be filled with more than 200 vendors of all sizes, from industry leaders Cadence, Magma, Mentor and Synopsys to emerging players Atrentra, CoWare, EVE, Jasper, GateRocket, Nusym and Real Intent. For a more complete list of verification vendors, check out the January 15 issue of DACeZine’s directory of verification tools:

www.dac.com/newsletter/shownewsletter.aspx?newsid=69

Register today to learn more about trouncing the verification challenge. I look forward to seeing you in San Francisco.

Andrew Kahng
General Chair
46th Design Automation Conference

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Note: This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. Register today to take advantage of early registration rates, available until Monday, June 29, at: www.dac.com

IEEE 1647 Call For Participation

Those of you who have been reading Cool Verification since the early days will know that I'm a big proponent of the e language.  The IEEE 1647 working group is looking for volunteers to help develop the next version of the e-language standard.  What follows is a letter from Serrie Chapman, a member of the IEEE 1647 committee.  If you have any questions please let me know and I'll pass them along to the appropriate committee members.

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Individuals interested in functional verification languages are hereby invited to take part in the 1647 working group effort. This effort is aimed at standardizing the e functional verification language. The e language has been evolving since it's introduction in 1996, and is used today by a large community of industrial and academic users.

We are currently working towards the P1647-2010 revision of the standard and the following widely used language features are part of this effort:

• Define-As-Computed
• Interface Ports
• Named Constraints
• Parameterized Types
• Real Data Type
• Temporal Coverage
• Type Constraints

Anybody with any interest in the e language could effect changes in the upcoming revision which could be of benefit to you. Consequently, I'm calling on new participants to help push this language forward by joining the IEEE Working Group for the e language yourself, or/and inviting any interested parties.

The good news is that it's very easy to participate: simply dial-in to an hour-long conference call once a month via a toll-free number setup for your home country. You can dive in and contribute to the discussion, or sit back and quietly monitor the group's progress.

Alternatively, a single message posted to the IEEE 1647 working group email reflector on a topic recorded in the minutes of the previous meeting is sufficient to qualify the author as attending the associated meeting. Either way, you will be able to ensure you & your company's needs will be captured in the standard.

The next working group meeting will be posted on the website and I welcome you or/and a colleague to dial-in to get a feel for the Group. The agenda, along with a list of world-wide toll free dial-in numbers, is posted here: http://ieee1647.org/agenda.html

If you want to join, please submit your details on http://ieee1647.org/join.html

And please let me know if you have any further questions.

Warm Regards,

Serrie Chapman

Member, IEEE 1647 Working Group

Last Minute Deal on SystemVerilog Training with Cliff Cummings in Beaverton, Oregon, 4/21-24

Those of you who attended SNUG in San Jose know that Cliff Cummings of Sunburst Design was a co-author on our award-winning paper on multi-stream scenarios in the VMM (honorable mention - technical committee award). Cliff (who won Best Paper at SNUG this year) has been a great friend and partner to myself and my colleagues here at Verilab.  As part of our continuing collaborative efforts, I’m planning on sitting in on Cliff’s SystemVerilog course next week in Beaverton, OR. 

Sunburst Design is offering Cool Verification promotional pricing of $2,200 for the 4-day Advanced SystemVerilog for Design & Verification Class or $1,650 for the 3-day Advanced SystemVerilog for Verification class.

To get this pricing, you must register at the web site:
http://www.sunburst-design.com/systemverilog_training/PROMO/

Also, as a special thanks from me for signing up with such short notice, I’m offering to present a new seminar I’m working on as private webinar to the first two registrants using the promotional link above[*].  Here’s the abstract of that material (subject to change):

Choosing a SystemVerilog base class library can be a difficult task, as it is not always clear what features are critical to enhancing productivity. EDA vendors heavily market their solutions but are not able to provide an unbiased viewpoint on the differences between their solutions and others. In this one hour presentation, JL Gray from Verilab will review the major features of the VMM and OVM and describe which features should be given the utmost consideration during the selection process. He will then delve deeper into key topics.

Cliff is also offering special pricing for displaced engineers seeking this or other Sunburst Design training. For details please visit the web site:
http://www.sunburst-design.com/DISPLACED/

If any of you are in the Portland area or can make it up there on short notice, I’d enjoy the opportunity to spend the week with you!

[*] Restrictions apply. Contact me for details.

SNUG Plug: Multi-Stream Scenarios and the VMM

Ok, I know what you’re all thinking… “JL, you haven’t even finished writing up DVCon yet and now you’re talking about SNUG?!” Yes, I know.  Let’s just say an annoying stream of illnesses have taken their toll on the Gray family (and many other folks as best as I can tell) over the last few weeks.  But things seem almost back to normal now and I didn’t want to miss out on an opportunity to let everyone know about my official debut as a conference paper presenter at SNUG San Jose next week. 

My Verilab colleagues Jason Sprott and Sumit Dhamanwala, along with Cliff Cummings from Sunburst Design and yours truly authored a paper entitled “Using the New Features in VMM 1.1 for Multi-Stream Scenarios”. I’ll be presenting the paper during session MA4: Verification with VMM I on Monday at 11am.  Those of you who attended one of the Verification Now 2008 seminars back in the fall will recognize the topic. I discussed the yet to be announced Multi-Stream Scenario additions to the VMM in one of my presentations. 

Unlike my Verification Now presentation which compared stimulus in the OVM to the VMM, the SNUG presentation will delve into the topic of Multi-Stream Scenarios in the VMM in more detail.  Specifically, I will review the following topics:

• Recap: Single Stream Scenarios
• Complex Stimulus with Multi-Stream Scenarios
• Multi-Stream Scenario Registries (Channel, MSS, and MSSG)
• Single Stream vs. Multi-Stream Scenarios
• Resource Sharing: Grab/Ungrab
• Multi-channel grab

One of the things I hope to touch on is the importance of using the registries when building multi-stream scenarios instead of directly instantiating sub-scenarios, channels, or scenarios from other multi-stream scenario generators (using the generator registry).  Those features were added to the MSS solution to allow integrators and test writers to modify the behavior of specific scenarios and scenario generators without having to modify the underlying scenarios themselves. 

Another goal is simply to promote the topic of reusable, multi-stream stimulus itself. The VMM has historically supported a flat testbench structure. New features such as MSS, when combined with the vmm_subenv should lead to more reusable and maintainable testbenches.

I’m thrilled to have an opportunity to present at SNUG this year and to meet readers of this blog and my Twitter feed.  I will be twittering SNUG using the hash tag #snug, unless someone gives me a good reason to use a different tag.  Of course, that begs the question – who will twitter my presentation while I’m presenting?  How about this… I will buy the person who Twitters the most insightful comments and/or questions during my presentation a delicious beverage of his/her choice. Any takers?

DVCon 2009 Wrap Up: Attendance

DVCon, the first big verification-related conference of the year is now complete. Unlike in past years where I’ve spent quite a bit of time during the conference blogging about what’s been going on each day, I’ve decided this year (as you may have noticed) to do a series of wrap up articles instead.  Why?  One big reason is that I was able to describe many of the minute by minute details of the conference on Twitter along with many of my new EDA Twitter friends.  More on that in a future post (or check out Karen Bartleson’s post on her Twitter experience at DVCon). Another reason is that I wanted to spend more time taking in the conference itself as opposed to huddled in a corner somewhere writing up blog articles. If you have any preferences for one over the other please let me know so I can make adjustments if necessary at DAC.

In this post I’m going to discuss conference attendance. Stay tuned for upcoming posts on Formal vs. Dynamic Simulation, industry moves towards improving constrained-random simulation, my theory that SpringSoft should eventually buy Jasper, the Wednesday “EDA: Dead or Alive” panel, and the use of Twitter at #dvcon.