Cool Verification

SystemVerilog 2012, DVCon 2010, and Travel

Now that the SystemVerilog 2009 standard has been released, the P1800 working group is getting ready to start work on the next version of the SystemVerilog standard.  As part of that effort, they are soliciting feedback in preparation for an open meeting on February 26 (the Friday after DVCon) where new features will be discussed (see also Brad Pierce's blog article on the topic).  Since you'll already be at DVCon (you ARE going to DVCon, right?), it should be easy to take the time to attend the IEEE meeting the next day.  Having said that, I'm going to miss the meeting as I'll be on my way to Shanghai to kick off a week of workshops in Asia, but one of my colleagues from Verilab may be attending.  

Speaking of DVCon, the early registration deadline is fast approaching.  Full conference registration is $485 before January 29.  After that, registration goes up to $565. The conference should be outstanding this year, despite the fact that I will be more actively involved than ever before ;-).  If you're planning to attend, please stop by and say hello at one of the following events:

• Monday Tutorial: Advanced Verification Techniques Using VMM - I'll be presenting for 45 minutes on the new phasing and factory features in the VMM 1.2.
• Wednesday Industry Leader's Panel: "What Keeps You Up At Night?" (stay tuned!)
• Thursday session 12.1: Stimulating Scenarios in the OVM and VMM - My favorite methodology topic now as a DVCon paper with my coauthor Scott Roland.
• Thursday Panel: Ever-Onward! Minimizing Verification Time and Effort - Somehow I managed to sneak onto this panel with this distinguished group of panelists. Come by and heckle me for a bit while the votes for best paper are calculated.

As a side note, I'll be traveling extensively in the next couple of months.  If you're located in any of the following cities, send me a note and perhaps we can catch up while I'm in town:

• Boston (this week!)
• Mountain View (next week)
• Irvine (next week)
• San Jose (for DVCon)
• Shanghai (first week of March)
• Taipei/Hsinchu
• Tokyo

Finally, if any of you are reading this and thinking - why isn't JL writing about something more interesting like, say, the UVM, please send me a note letting me know. I've had blog writer's block/burnout for the last few months and could use the encouragement ;-).

As a potential user of the UVM, would you like to be able to view active development branches within the live UVM repository, or should this information be hidden until official releases are made?

Yet another Accellera call about the Unified Verification Methodology (UVM) is underway. My takeaway? Both EDA and user companies put such a premium on secrecy that a truly open development process is simply not possible. Based on its current trajectory, the EDA vendors appear to have the desire to have a preview of potential innovations before they may be shared with the Accellera committee. Why? Because the only people capable of discussing certain aspects, such as **log files** of EDA vendor tools are the vendors themselves.

The Relevance of Formal Methods

In a fascinating (to me) twist of fate, I will be moderating a panel on the “next big thing” in formal methods at FMCAD 2009 in Austin, Texas. The panel, entitled “What will be the next breakthrough solutions in formal?” is being held from 11:50-14:00 on Wednesday, November 18, and is made up of four distinguished panelists:

• Harry Foster, Mentor Graphics
• Ziyad Hanna, Jasper Design Automation
• Kevin Harer, Synopsys
• Axel Scherer, Cadence

Those of you who have been reading Cool Verification for awhile will note that I have never really discussed the topic of formal methods on this blog.  Truth is, I’ve yet to come across a situation on a project where I needed to use formal to get the job done. My theory is that there are a couple of issues preventing wide-spread adoption of formal tools in a standard verification flow.  First, the impression I get is that using formal well requires special expertise to write appropriate properties, partition the design, and interpret the results of the tools.  Second, the fact that you need special tools at all. In other words, the fact that I need a separate tool in my flow other than Questasim, VCS, or IUS (not to mention a separate license) makes it difficult for someone to try out formal techniques outside the tool flow of a typical project.

During the panel I plan to ask panelists about just such issues, plus several other questions proposed by thoughtful engineers just like you on the Google Moderator site set up for just this purpose.  In fact, I’d like to request your assistance. If you have a question you’d like to see asked of one of the panelists please submit it (or vote on your favorites) via the Google Moderator site or by mailing me directly at jl at coolverification dot com. 

I’m also quite interested to hear any stories readers may have with respect to the adoption (or lack thereof) of formal tools in your respective companies and current projects.  There are several types of formal tools out there… Any types of tools you’ve had great success with in particular? Or great failures? Does the choice of formal technique heavily depend on the application domain in question? What do you think the EDA vendors need to address in tool functionality/usability in order for you to consider adopting formal more broadly?

And of course, if you’re planning on being in Austin for FMCAD please let me know!

The Past, Present and Future of the Design Automation Conference

It’s over. After weeks of preparation (on my part, a year on the part of countless others), and a week of staying up late then getting up early, the 46th Annual Design Automation Conference has finally come to a close.  One of the main highlights of the conference was the Synopsys-hosted Conversation Central interactive forum on social media.   I also enjoyed my opportunity to participate on a Pavilion Panel on “Seeking the Holy Grail of Verification Coverage Closure”, to present the new VMM 1.2 updates in the Synopsys theater, and to give a presentation entitled “Zero to Sequences in 30 Minutes” in the OVM World booth.  Special thanks to all of you who spent time talking with me on Monday and Tuesday sharing your thoughts with me on that topic to help me prepare for the panel.  And of course, there was the ever-enjoyable Denali Party (click here for pictures)!

Throughout the conference though, I had a nagging suspicion that I was missing some perspective on where we’ve been as an EDA industry, where we are currently, and where we’re going in the future.  This being only my third DAC, it wasn’t clear to me if anyone was around from the earlier days who would be able to help me fill a gap in my industry knowledge.  After asking around, I quickly realized that I needed to speak with Marie and Pat Pistilli, founders of the aptly named MP Associates and organizers of the very first DAC back in 1964 (and every DAC since).  At the time, DAC was, according to Pat actually called SHARE, which stood for the “Society to Help Avoid Redundant Effort”. 

Pat Pistilli, MP Associates

I was able to arrange a time to meet with Pat on Wednesday evening before the DAC party.  I wasn’t really sure what to expect, and Google wasn’t much help.  So naturally, I asked Pat to tell me about his background and how he ended up founding DAC. In the late 50s Pat was working at Bell Laboratories on a project called “Safeguard”.  (For info on Safeguard, check out the ever-useful Wikipedia. Also, this site dedicated to the Mickelson Safeguard Complex contains a list of references that appear to be relevant).  The idea of the project was to create a computer that could quickly identify which Soviet ICBMs were duds and which were real during a nuclear attack.