Cool Verification

UVM and the Death of SystemVerilog

Earlier this year, the Accellera VIP-TSC approved version 1.0 of the UVM. Supported by all of the major EDA vendors, the UVM has been billed as the next generation in verification methodology goodness. Better than the VMM. Better than the OVM. A chance for the verification community to shed some of the baggage carried over from years of backward-compatibility requirements and methodology fits and starts. Another purported benefit is that testbenches written with SystemVerilog/UVM can be more easily ported to simulators from different vendors. There is also a developing market in UVM verification IP to allow testbenches, in theory, to be quickly constructed from commercially available components.

All of this sounds great, right? Vendors standardizing on languages and methodologies and competing on tools. It's how the world should be. Except there are a few small problems that vendors are unlikely to tell you about before you start your next project.

First and foremost is a problem that is glaringly obvious to anyone who's tried learning SystemVerilog and the UVM (or one of the other VMs over the years): it's difficult and time consuming to learn SystemVerilog and any of the VMs... especially if you have never used a verification language before.  Folks with limited software backgrounds (read: most design and verification engineers) find seemingly simple concepts like inheritance and factories to be mind boggling, even if they won't admit it. And folks with deep software backgrounds will find SystemVerilog an absolute pit of despair when compared with modern languages such as Python and Ruby, and the UVM complex in a way that clearly is meant to patch over serious deficiencies in the underlying language. Plus, any testbench that has to deal with multi-language issues is clearly out of luck in the simplicity and ease of use department.

Now that the UVM has arrived and the methodology bickering between the major vendors has mostly (well, somewhat) ceased, the complexity of the UVM and the earlier VMs on which it is based can be viewed more clearly and with less controversy. And the results are not good.  After years of experience working with many multiple clients, it seems the only way out of our current dilemma is to start looking at other languages and development frameworks. For that to happen, major semiconductor companies may need to start funding this type of development again, since it is abundantly clear the EDA vendors are incapable of this level of innovative thinking. Or more kindly, perhaps they feel there is no money in innovation. Either way, major advances in design and verification productivity need to get here sooner rather than later.  

48th DAC Day 1: Cloud Computing, Registers

This marks my 5th year attending the Design Automation Conference. Unlike prior years where I've lugged around my camera and had a schedule of events to participate in, this year, I came with a relatively free slate. No hard plans, just a todo list (thank goodness for OmniFocus for iPad) and my walking shoes. I wanted to share a quick list of a couple of my highlights from Monday. 

As usual, my first few hours at DAC involved me wandering the show floor catching up with all of my friends and colleagues that I only get to see in person at conferences. Included in that list were Harry Gries and James Colgan, who were kind (and patient) enough to give me demo of Xuropa's latest cloud offerings in the Synopsys Partner's booth. I've been struggling with the benefits of EDA in the cloud for a few years now, but have recently seen some good use of outsourcing one's EDA IT infrastructure. But the product Xuropa (and Synopsys - more later) is pushing is a bit different than what I've been used to up to this point.

Project Planning Birds-of-a-Feather at 48th DAC?

Quick question for those of you attending DAC next month. Would anyone be interested in working with me to organize a project planning/management Birds of a Feather session? I've been dabbling in Agile techniques for the last several months and would enjoy sharing experiences with others about what project planning and management techniques (Agile or otherwise) work best.

Let me know via blog comment, Twitter, or email at jl at coolverification dot com.

 

Cool Verification on Facebook, Twitter

As many of you have noticed, I've fallen into quite an irregular posting schedule here on Cool Verification. After almost 6 years I don't feel too bad about not having a post up ever week (um, well, once a quarter?). But one reason for the irregular posting schedule is that I've been communicating much more heavily with many of you via Facebook and Twitter. If you'd like to join in the conversation, I'd recommend you head over to one of the following sites and "like" or "follow" me to participate!

• Cool Verification on Facebook
• JL Gray on Twitter

As a side note, I've got an audio recording of my "Making Great Products Great" panel from last week. I'm trying to work out the best way to post it. If you have suggestions on how to do it (beyond embedding a streaming link in a blog post) let me know.

Free Panel, and Photos from DVCon 2011 Day 2

Just a reminder, my Wednesday panel "Making Great Products Great" is free and open to the public. You just need to register for a free "Exhibit Only" pass either on the DVCon website or at the registration desk at the conference.

Also, for your viewing enjoyment, here are some photos from Day 2 of DVCon.